When writing data into a synchronous DRAM (Synchronous Dynamic Random Access Memory, hereinafter referred to as a SDRAM) or reading data from the SDRAM (hereinafter referred to as data access), it is difficult to make appropriate timing because of a high-speed operating clock. Therefore, conventionally, a LSI that makes data access to the SDRAM is fabricated initially, and then the phase of the clock is adjusted by trial and error.
Further, Japanese Published Patent Application No. Hei.9-185427 discloses a clock phase adjustment circuit and a clock phase adjustment method for making timing of access to a SDRAM.
FIG. 13 is a circuit diagram illustrating a memory interface circuit to which a clock phase adjustment circuit as disclosed in Japanese Published Patent Application No. Hei.9-185427 is applied. A memory interface device 700 comprises a clock frequency converter 710, two input buffers 711 and 720, a clock phase adjustment circuit 712, three output buffers 715, 717, and 719, and three flip-flops (FF) 716, 718, and 721. The interface device 700 outputs an external clock signal, a SDRAM command, and data to a SDRAM 702.
The clock phase adjustment circuit 712 is a circuit for adjusting the phase of a clock signal to execute appropriate data access to the SDRAM 702, and it inverts the phase of a clock signal as a reference of operation by 180 degrees, and outputs the clock signal to the SDRAM 702. The clock phase adjustment circuit 712 is composed of an inverter 713, a phase converter 714, and a selector 744.
The phase converter 714 is provided with clocks having different delay values. After the memory interface device 700 is connected to the SDRAM 702, operable clocks are tested by appropriate means, and a clock, which is judged as being appropriate on the basis of the result of the text, is selected.
The conventional clock phase adjustment is carried out by trial and error after fabricating an actual LSI. That is, since the design engineer adjusts the clock phase by repeating trial and error after the LSI is fabricated, the process steps relating to the fabrication of the LSI are complicated.
Further, in the interface device 700 as disclosed in Japanese Published Patent Application No. Hei.9-185427, a lot of delay elements relating to clock phase adjustment are required, whereby the circuit scale is increased, and the power consumption is also increased.
Further, since the data inputted to the interface device 700 passes through various circuits and buffers before it is outputted from the device 700, when the interface device 700 is implemented in a practical LSI, the delays of clocks might be greatly different from those expected, resulting in difficulty in determining the delay values of the delay elements. In this case, although determination of the delay values may be facilitated by preparing more delay clocks, this causes a new problem that the circuit scale and the power consumption are further increased.
Furthermore, since the delay values cannot be known unless the interface device 700 is actually connected to the SDRAM 702, it is necessary to perform, after connecting the interface circuit 700 to the SDRAM 702, a test of data transfer to select a clock of optimum delay value, whereby the number of process steps relating to the circuit fabrication increases.
Moreover, since external factors (wiring delay, external load, etc.) are not considered in the interface device 700, the precision is degraded. Further, in order to consider the external factors, a test of data transfer must be performed for every substrate to select a clock, whereby the number of process steps relating to the circuit fabrication increases.
The present invention provides a clock phase adjustment method that realizes clock phase adjustment in the designing stage, with reduced number of process steps relating to fabrication of a device that makes access to an external memory, without performing phase adjustment by trial and error, and without performing a test for clock phase adjustment. This clock phase adjustment method realizes supply of more reliable clocks, with minimum required circuits, even in perfect synchronous design, and realizes automatic clock phase adjustment even when a feedback clock system is employed.
Further, the present invention provides an integrated circuit and a design method thereof, which realize data access on the basis of a high-speed operating clock, without requiring complicated structure like the conventional circuit.